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A comment on A review of endianness bugs in Qt, and how they were fixed. Parent comment

Re:A review of endianness bugs in Qt, and how they were fixed by conistonwater on Saturday January 02, 2021 @06:09AM (#25611980)
I clicked around a little, and it seems "icc 21.1.9", "x64 msvc x19.28", "risc-v clang (trunk)", "armv7-a clang (trunk)" compile it to four separate byte loads, it looks like. It's not that I don't trust my compiler (usually clang) to optimize it this way, it's just that the level of variability between compilers makes me think I shouldn't really rely on this behaving this way.

I wonder what the arch difference is between the clangs that do it and the ones that don't, I don't know much about arm and risc-v.

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Re:A review of endianness bugs in Qt, and how they were fixed by user-the-name on Saturday January 02, 2021 @06:53AM (#25612172)
ARM does not support non-aligned reads, and can not safely change four byte loads into a one 32-bit load unless it can guarantee the address is aligned to 4 bytes.

Not sure about RISC-V but I would not be surprised if the same applies there.

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Re:A review of endianness bugs in Qt, and how they were fixed by pm215 on Saturday January 02, 2021 @07:27AM (#25612344)
It used to be the case that Arm could not handle unaligned loads, but that functionality was added in v6 of the architecture (many years ago now) and so is present in most Arm cores around today including all the 64-bit ones.

(Some instructions insist on aligned data, like atomic read-modify-write operations and some types of SIMD insn, but x86 has a few needs-alignment special cases too. Basic "just load/store data" insns that the compiler will emit are fine.)

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Re:A review of endianness bugs in Qt, and how they were fixed by shakna on Saturday January 02, 2021 @07:13AM (#25612262)
> Not sure about RISC-V but I would not be surprised if the same applies there.

It's probably a case of lowest common denominator.

Unalligned access is discouraged but allowed by the spec... But it's allowed to raise an exception. But not required. Cheaper to optimise to avoid that circumstance.

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