This was explored in detail in another thread, it seems most of the gains are from looser memory ordering.

I think that Apple "just" [1] picked a very happy place in the parameter space: lower clock means that main memory (which is already lower latency than usual) is "nearer" to the cpu plus a larger L1 with a shorter latency (3 cycles). These (plus probably a larger amount of sustainable outstanding misses) imply that the cpu stalls less which means that they can sustain a larger ILP [2]. A better branch predictor (which is rumored to be best in class, although I haven't seen any in depth analysis) means that they can usefully have a larger reorder buffer and extract even more ILP and memory level parallelism. Finally the large width can take advantage of the extracted parallelism.

The weaker memory model should help extracting additional memory level parallelism, but I doubt that ordering has large impact. M1 is quite good even when running in TSO mode.

[1] of course they need to be commended for this, they went against the usual wisdom, probably because their CPU was designed to be low power first then high performance, not the other way around.

[2] typically the average ILP for normal applications is 1.5 instructions per cycle, but the variance is high, so if you reduce the amount of cycles the cpu is stalled, the ILP can go up fast.

I agree with the rest, but memory latency is actually pretty poor on the M1:

https://www.anandtech.com/show/16252/mac-mini-apple-m1-teste...

You’re right. Like I said, atomics are one space. Another as you point out is that the memory architecture is pretty unique at providing high throughout and lower latency than traditional x86 architectures. I suspect Intel and AMD will adjust their roadmaps accordingly as a result of this new competition.

Where does the low-latency claim come from? Benchmarks do not validate it, giving main memory latency of around 100 ns.

Apparently you are right, but because of the lower clock, main memory is still closer in cycles. It would also be interesting to know the amount of outstanding main memory references.

By the way, does someone knows where RISC-V stands regarding this ?

Yes I agree, it's more the semantics and the legacy of x86 (page sizes, MMU, memory models - even though Rosetta still runs faster than x86) than simply decoding.