M1 is a clear example of something a lot better where competitors are unable to keep up or adapt.
Yet tons of people in this thread still make up (bad) reasons why Intel/AMD have nothing to worry about.
I remember similarly dumb arguments about the iPhone too in 2007. Some people are just unable to recognize major change even when it's blindingly obvious.
Status quo bias is strong.
That’s…emulation.
First line from Wikipedia[1]:
Rosetta is a dynamic binary translator developed by Apple Inc. for macOS…
Follow the link for Dynamic Binary Translator[2]:
Dynamic binary translation (DBT) looks at a short sequence of code—typically on the order of a single basic block—then translates it and caches the resulting sequence. Code is only translated as it is discovered and when possible, and branch instructions are made to point to already translated and saved code (memoization).
Dynamic binary translation differs from simple emulation (eliminating the emulator's main read-decode-execute loop—a major performance bottleneck), paying for this by large overhead during translation time. This overhead is hopefully amortized as translated code sequences are executed multiple times.
[1]: https://en.wikipedia.org/wiki/Rosetta_(software)
[2]: https://en.wikipedia.org/wiki/Binary_translation#Dynamic_bin...
Rosetta absolutely is an emulator, which has traditionally referred to taking code from one CPU architecture and making it run on another (in contrast with taking a binary of the same architecture but running it in another environment, which is often called a "compatibility layer" or in Apple's terms a "simulator", or the hardware-assisted version of this which is virtualization). There are many ways to write the part of an emulator that mimics another CPU; the simplest is an interpreter loop, but there's ahead-of-time and just-in-time code generation techniques as well. Dynamic binary translation is quite simple, as your quote mentions; Rosetta 2 instead achieves its performance through a combination of static binary translation to a form amenable to its runtime. Things that it cannot translate go through a fairly advanced optimizing JIT that goes way beyond what a dynarec would typically do.
We don't know what the efficiency will look like after you add all the I/O you need for a real desktop, we don't know how the memory subsystem will deal with 4 more cores that are just as fast. What's the point of having fast cores if you cannot feed them?
We don't know how lower yields for bigger chips on the newest nodes will affect their costs.
People act like Apple changed the game or is light years ahead of everyone but they literally haven't made a proper desktop-class chip yet. It's not because they don't care about higher core chips or chips with proper IO. They haven't made them because they CAN'T (yet).
So yes, Apple does have catching up to do.
That wouldn't be good enough for production hardware. The developer units had a previous iPad’s A12 SoC in an enclosure for developers to test things on. For example, the A series doesn't support virtualization because that's not required on a phone or tablet. But the M1 supports this and other laptop/desktop features. Even the A14 only has 4 cores compared to the M1's 8 cores. This isn't just a tablet SoC.
We don't know what the efficiency will look like after you add all the I/O you need for a real desktop, we don't know how the memory subsystem will deal with 4 more cores that are just as fast. What's the point of having fast cores if you cannot feed them?
Perhaps you haven't been paying attention, but the Mac mini is a real desktop. And all of the M1 Macs have blazingly fast memory access. Remember, it's an SoC—the memory is on the same die as the CPUs, GPUs and they all have equal access to it. No bus to go across. That's why it's so fast.
People act like Apple changed the game or is light years ahead of everyone but they literally haven't made a proper desktop-class chip yet.
The M1 already has features no "desktop" chip has, such as 8 instruction decoders. This may not sound like a big deal, but none of the Intel or AMD chips--not the threadripper or the Zen3—has more than 4. Why this matters:
"It is because the ability to run fast depends
on how quickly you can fill up the ROB with
micro-ops and with how many. The more quickly
you fill it up and the larger it is the more
opportunities you are given to pick instructions
you can execute in parallel and thus improve performance.
Machine code instructions are chopped into micro-ops
by what we call an instruction decoder. If we have more
decoders we can chop up more instructions in parallel
and thus fill up the ROB faster.
And this is where we see the huge differences.
The biggest baddest Intel and AMD microprocessor
cores have 4 decoders, which means they can decode
4 instructions in parallel spitting out micro-ops.
But Apple has a crazy 8 decoders. Not only that
but the ROB is something like 3x larger. You can
basically hold 3x as many instructions. No other
mainstream chip maker has that many decoders in
their CPUs."
"However on an x86 CPU the decoders have no clue
where the next instruction starts. It has to
actually analyze each instruction in order to see
how long it is.
The brute force way Intel and AMD deal with this
is by simply attempting to decode instructions at
every posssible starting points. That means we have
to deal with lots of wrong guesses and mistakes which
has to be discarded. This creates such a convoluted
and complicated decoder stage, that it is really
hard to add more decoders. But for Apple it is
trivial in comparison to keep adding more.
In fact adding more causes so many other problems
that 4 decoders according to AMD itself is basically
an upper limit for how far they can go.
*This is what allows the M1 Firestorm cores to
essentially process twice as many instructions as
AMD and Intel CPUs at the same clock frequency.*"
"As far as I remember from performance benchmarks
the newest AMD CPU cores, the ones called Zen3
are slightly faster than Firestorm cores. But
here is the kicker, that only happens because the
Zen3 cores are clocked at 5 GHz. Firestorm cores
are clocked at 3.2 GHz. The Zen3 is just barely
squeezing past Firestorm despite having almost
60% higher clock frequency.
So why doesn’t Apple increase the clock frequency
too? Because higher clock frequency makes the chips
hotter. That is one of Apple’s key selling points.
Their computers unlike Intel and AMD offerings barely
need cooling.
In essence one could say Firestorm cores really
are superior to Zen3 cores. Zen3 only manages to
stay in the game by drawing a lot more current and
getting a lot hotter. Something Apple simply chooses
not to do."
Come again?
The Zen3 barely beats the M1, which runs at 60% of the speed and a small fraction of the power. It can essentially process twice as many instructions at the same clock frequency. They're already ahead in many key areas, with performance per watt being the most obvious. There are issues with the x86 architecture, like instructions ranging from 1 to 15 bytes, which limits Intel and AMD from being able to process as many instructions per clock cycle as ARM processors in general and the M1 especially.
I’m quoting from the article "Why is Apple’s M1 Chip So Fast?", which has a lot more technical details: https://erik-engheim.medium.com/why-is-apples-m1-chip-so-fas...
> And all of the M1 Macs have blazingly fast memory access. Remember, it's an SoC—the memory is on the same die as the CPUs, GPUs and they all have equal access to it. No bus to go across.
What does this even mean? Memory works at a certain voltage, clock speed, and has a capped rate at which it can transfer data if those are kept constant. For DDR4-3200 it's generally 3,200 MTs (megatransfers/sec).
What does every core has equal access to it mean? What does soldering SDRAM change in terms how many transfers/sec it can do? What do you mean there is no bus?
> The M1 already has features no "desktop" chip has, such as 8 instruction decoders.
What makes going wide a "desktop" class feature? Going wide isn't free, there is transistor cost associated. A M1 chip has 16 billion transistors for 8 cores. AMD's EPYC Rome has 39.54 billion transistors for 64 cores. That's 8 times as many cores. And that's including ~9 billion transistors just for the I/O die.
If you look at just the chiplets, AMD's 8 Core complexes take up only 3.9 billion transistors each. And these are 8 high performance cores with SMT, even removing GPU/NPU engines from M1, AMDs design clearly has a lower transistor cost.
> The Zen3 barely beats the M1
AMD was't trying to make an entry level laptop chip, so it's not good at being a entry level laptop chip? How do you think M1 would fare if we try to compare them on datacenter CPU metrics?
I understand why everyone is excited, but they aren't looking at the whole picture.
I’ll just hit the obviously erroneous issues here.
A M1 chip has 16 billion transistors for 8 cores. AMD's EPYC Rome has 39.54 billion transistors for 64 cores.
It doesn't make sense to compare the M1 with the EPYC Rome. They couldn't more different and were developed for dramatically different use cases.
(I also don't think it's not a good look when folks feel compelled to state Apple's M1 isn't as fast as AMD's $4000 64-core processor, as if this means anything. Of course the EPYC Rome is faster--duh. Anyways…)
16 billion transistors on the M1 SoC (emphasis on system) gets you an 8-core GPU, a 16-core Neural Processor, a Digital Signal Processor, a Secure Enclave, image processing unit, video encoder/decoder and of course 8 CPU cores and 8 or 16 Gb of memory.
Instruction decoders deal with the out of order execution of the instructions; more decoders enables you to have more instructions "in flight" as they say for the execution cores to run in parallel.
Again, you should read the article for the details, but due to the legacy architecture and technical debt of a 40 year-old instruction set, not to mention with instructions ranging in size from 1 to 15 bytes, it's not easy for the decoders to juggle all of the instructions to do out of order execution of instructions. Yes, even the EPYC Rome only has 4 instruction decoders.
Meanwhile, the instructions for Apple's Firestorm cores are all the same size, making decoding the instructions much easier and faster; so much so that the M1 has 8 decoders, which is unheard of in a mainstream processor.
Here's the bottom line quote from the article: "In fact, adding more causes so many other problems that four decoders according to AMD itself is basically an upper limit for how far they can go. This is what allows the M1 Firestorm cores to essentially process twice as many instructions as AMD and Intel CPUs at the same clock frequency."
Apple and AMD solved the "get as many instructions in the pipeline as possible and process them as quickly as possible" problem two different ways.
AMD does it with threading and many cores; Apple does it by increasing the number of instruction decoders and by having 60+ Gb/s bandwidth with a 128-bit bus. Apple didn't implement SMT because they don't need it; they have no issues with keeping their instruction pipeline full.
Bottom line: Apple's approach has more headroom than AMD's approach. They can't add more instruction decoders, so they crank up the clock speed and the threads to execute more instructions per clock cycle. But the M1 is so efficient, it processes twice as many instructions at the same clock frequency.
The M1 runs at 3.2 GHz; it's got a higher ceiling because Apple can add more cores and increase the clock speed a lot before it gets anywhere near the power consumption and other physical limits that AMD is starting to run up against.
[1]: https://debugger.medium.com/why-is-apples-m1-chip-so-fast-32...
The author of your beloved article compared M1 to Zen 3, and all Zen 3 CPUs use the same 8-core chiplet. From the cheapest 6-core Ryzen 3 5600 to the 64 core EPYC. All of them are made of the the exact same chiplets, just then number of chiplets varies. If you have 2 chiplet you get 16 cores, etc.
> Yes, even the EPYC Rome only has 4 instruction decoders.
It doesn't have "4 decoders"; it's just one 4-way instruction decoder. It's not the same thing.
> Firestorm cores to essentially process twice as many instructions as AMD and Intel CPUs at the same clock frequency.
A decoder doesn't not process instructions, it only interprets them and splits it up into smaller instructions. It doesn't make sense to compare number of instructions across different ISAs anyway, ARM has smaller, simpler, and on account of that more numerous instructions. One x86-64 instruction more often than not maps to multiple ARM instructions. It just makes no sense to compare counts.
I sort of stopped reading your comment around here, sorry about that.
Apple’s Rosetta 2 doesn't do emulation; it translates the x86 code into ARM code on the fly and runs it, which is why most apps run faster on M1 Macs than they do on Intel Macs--and comparably priced PCs.
Now that it has happened, we will likely see more from the PC industry.
Probably not. If Intel and AMD were capable of this kind of performance per watt, they’d already be doing it. Years ago.
Because the latest x86 chip has to be backwards compatible with 40 years of legacy code, there are certain limitations Intel and AMD just have to live with.
Apple will likely have a hard time keeping up unless they have more up their sleeve.
It's ironic that it's Apple that will have a hard time keeping up when they've already disrupted Intel and AMD. Remember, it's not just a processor; it's a system on a chip that contains an 8-core GPU, 16-core Neural Engine for machine learning tasks and other components.
This has obviously been in the works for several years; Apple wouldn't have gone down this path if they didn't believe it would give them a sustainable competitive advantage for years to come.
Even with its ridiculous performance, the M1 is the entry-level consumer version of the M series suitable for (in Apple's lineup) entry-level consumer hardware. The M1-based MacBook Air doesn't have a fan and it's faster and more capable now than many (most?) PCs that cost more and run hotter.
One thing we know: the M2 will be faster and more capable than the M1 and won't be limited to 16 Gb. We'll probably see M2-based Macs by the summer of 2021.