I brought up the first ever 110nm node and it was based on the memory half-cell width in a standard way that we didn’t use because it didn’t functionally scale down to that size anymore, but the lithography equipment could make something that passed Intel’s TEM inspection according to expert analysis. So, from what I understand, not since Intel left the DRAM business.

Problem is that gate design itself changed.

Was that FinFET? And is 3nm gate-all-around?

There was quite a variety of MOSFET before FinFET, it yeah, that was a hard right turn.