I think I found the answer in this tweet.

https://twitter.com/Catfish_Man/status/1326298205034696705

Heres a snipped quote.

"this further improvement is because uncontended acquire-release atomics are about the same speed as regular load/store on A14"

x86 has total store order, all stores are queued(store buffer) in the CPU and then pushed to the cache subsystem. Last item has to wait previous ones. Arm doesn’t have TSO, so CPU can reorder stores in the queue or issue stores out of order etc. depending on memory barrier use.

If you read the Catfish_Man tweet, he says that even under rosetta refcounting is faster, and under rosetta M1 has TSO.

It’s much more than twice as fast.

https://twitter.com/catfish_man/status/1326238434235568128?s...

What's the actual optimization though?

The tweet author in the linked thread later writes:

"Weaker memory model makes acquire-release atomics possible to implement much more efficiently, in exchange for not hiding some classes of multithreading bugs"

Have you read the tweet and thread? If so, I don’t understand what you’re asking.

Twitter wasn't making the relevant responses really visible. _kbh_ pointed it out