What is a System-on-Chip (SoC), and why do we care if they are open source?

Re:What is a System-on-Chip (SoC), and why do we care if the... by rektide on Monday November 09, 2020 @04:14PM (#25040000)

As the other comments say, it's going to cost a million bucks probably to get something made. I wouldn't be shocked to hear numbers way lower for some smart folks. I wonder, for example, what it cost GreenArrays to get their chips made, how big their run was. But $1M i probably a pretty safe ballpark starting place.

And we have pretty great open source cpu & ram design tools. MAGIC is free. There's a lot of great tools fora lot of this.

What is not so great is all the un-core. And GPU, if you want that.

The SiFive boards were coming with TileLink[1] as the main way to talk to the core, for a while, I believe, which is a pretty low level cache-coherent fabric used no where else. There's decent off the shelf to design a lot of the digital systems here. But I don't know what resources if any are available to help you build a chip-to-chip interface, to expose the TileLink. And there's basically the world's tiniest market for things to plug in on the other end anyways.

When you buy an SoC, almost all embedded folk expect a bunch of semi-standard capabilities. I2C, I2S, DisplayPort, USB, Ethernet, &c are all common things you might want. While we can make a decent cpu now a days, afaik, we are still in very very very early days, very pre-implementation, for almost all of these. Thusfar almost everyone relies on buying closed IP to provide connectivity for the SoC they are making. It's quite likely to be the case as well for the new SiFive Unmatched board; I expect they bought someone's PCIe IP & integrated it.

We are starting to see more neat work with FPGA implementations of various protocols like USB3 & PCIe but these all rely on the FPGA having really good transceivers that tackle the PHYsical layers, do the dirty work. Building actual transistors to be receivers & transmitters into & out of the chip, that's where, atm, we are all but babes, it feels like.

[1] https://www.youtube.com/watch?v=EVITxp-SEp4

[ Parent | on HN ]

Re:What is a System-on-Chip (SoC), and why do we care if the... by rektide on Tuesday November 10, 2020 @02:53AM (#25043685)

> What's more, SoCs incorporate components from a small number of vendors supplying designs for USB, DDR, and PCI controllers: "this means the same disused logic motifs are baked into hundreds of millions of devices, even across competing brands and dissimilar product lines."

https://mamot.fr/@pluralistic/105183378364921755

I really think this is the killer point of it all. The cores are the easy part. The digital part. Are we making headway anywhere else? Eh, yes, a tiny bit? Barely?

[ Parent | on HN ]

Re:What is a System-on-Chip (SoC), and why do we care if the... by nereye on Monday November 09, 2020 @07:32PM (#25041665)

On the other hand, https://www.efabless.com/ offers:

$70K 20 WEEKS 100 SAMPLES

[ Parent | on HN ]

Re:What is a System-on-Chip (SoC), and why do we care if the... by egsmi on Monday November 09, 2020 @07:45PM (#25041734)

Don’t get me wrong, I think what those guys are doing is cool, but it’s 130nm, a fairly small die, and it’s not a fully custom ASIC. That’s how they’re getting the cost down to under $100K. “Degree of Customization: Only what is available through configuration of the design template”

[ Parent | on HN ]

Re:What is a System-on-Chip (SoC), and why do we care if the... by bunnie on Tuesday November 10, 2020 @01:36AM (#25043336)

Thanks for pointing that out. Yes, the $1mm number I cited in my post is the estimated raw cost of a full mask set for a relatively modern process in the 2Xnm or smaller range.

Definitely older processes have much cheaper mask sets -- in part because there are just fewer metal layers, and fewer & cheaper masks required to image the transistors when the wavelength of light used (193nm) is close to the line width of the devices themselves.

[ Parent | on HN ]