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A comment on An ex-ARM engineer critiques RISC-V. Parent comment

Re:An ex-ARM engineer critiques RISC-V by bshanks on Saturday November 07, 2020 @11:06PM (#25022843)
If the destination of sov is specified to always be tflags, then you may as well combine add and sov into one instruction, with tflags implicit:

addsov t2, t1, t0

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