Re:An ex-ARM engineer critiques RISC-V
by brandmeyer on Sunday November 01, 2020 @05:59PM
(#24963307)
You have a typo: size_t doesn't need zero extension. RISC-V does have 32-bit signed integer arithmetic that unconditionally sign-extends the result from bit 31. So using a signed integer as a counter (bad practice IMO, but widely recommended in style guides) doesn't need anything extra at all.
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