An ex-ARM engineer critiques RISC-V

Re:An ex-ARM engineer critiques RISC-V by IshKebab on Sunday November 01, 2020 @05:21PM (#24963049)

> The idea is that high end processors will recognise these sequences

I'm not sure that is the idea, given that RISC-V is targeted at processors so low-end that they don't even implement multiply.

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Re:An ex-ARM engineer critiques RISC-V by audunw on Monday November 02, 2020 @03:53PM (#24973188)

That’s not true. RISC-V targets the full spectrum of processors (well, not 8/16-bit, so not the very low end). Some of the decisions they made, compared to say OpenRISC is made just to make the ISA easier to implement with superscalar CPUs (not having branch delay slots)

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