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Re:An ex-ARM engineer critiques RISC-V by jcranmer on Sunday November 01, 2020 @12:30PM (#24960995)
You have to preserve the architectural registers at the end of the sequence. So if there are 5 registers, you either have to have a 5-register microinstruction, or issue multiple 3-register microinstructions instead.
Re:An ex-ARM engineer critiques RISC-V by ithkuil on Sunday November 01, 2020 @04:20PM (#24962597)
You have to preserve architectural registers only when some other instruction actually depends on them. When you detect a dependency you lazily compute their content (causing a stall)
Re:An ex-ARM engineer critiques RISC-V by brucehoult on Sunday November 01, 2020 @05:26PM (#24963090)
The dependency could be arbitrarily many millions of instructions away.

The only way to know there isn't a dependency is if that register gets clobbered by something else very soon afterwards.

But this whole topic of "checking for signed overflow is expensive" is overblown. It's simply not that important an operation, especially in the context of those languages that do it a lot also doing a lot of memory references, which are far more expensive.

Adding arbitrary completely unknown integers is pretty rare. If you know both numbers are greater than zero then a single compare-and-branch is all you need. If one of the numbers is a constant then a single compare-and-branch is all you need.

Re:An ex-ARM engineer critiques RISC-V by jcranmer on Sunday November 01, 2020 @05:32PM (#24963127)
That sounds like an amazingly bad idea, because you would instead have to retain the two source registers until you can prove that you don't need the two output registers anymore, which can be arbitrarily far in the future.