I don't think the instruction sequence from the article would qualify for macro-op fusion. Berkeley looked at this for the simplest case of LEA [1]:

  // &(array[offset])
  slli rd, rs1, {1,2,3}
  add  rd, rd,  rs2

The sequence in the article uses what Intel calls the fast case but it still wouldn't qualify for Berkeley's two instruction fusion. Dunno if anyone does three instruction fusion.

As an aside, LEA is never getting added to the base RISC-V nor should it be. But I'm surprised it isn't considered for an extension.

[1] https://www2.eecs.berkeley.edu/Pubs/TechRpts/2016/EECS-2016-...