Thanks for the reply but I'm not sure what you mean. Are you saying you want to add an i32 to a u64? Or am I completely misunderstanding? I'm not sure why unsigned-unsigned or signed-signed instructions would be hard. Idk about mixed sign operations, but when do they ever occur without first casting one to the other?
Re:An ex-ARM engineer critiques RISC-V
by pizlonator on Sunday November 01, 2020 @12:30PM
(#24960996)
I mean you will do overflow checks on the following. I’ll use the “s” and “u” prefixes to mean signed and unsigned. Unsigned matters less than signed.
sadd32, sadd64, uadd32, uadd64, ssub32, ssub64, usub32, usub64, smul32, smul64, umul32, umul64
Ah, I get you now. Yes, this looks like a weak point, and I totally get why it'd screw with Javascript optimizations.
I don't think it's a fusion problem; even if you did fuse these sequences, they'd still be bad, since they'd be writing lots of extra registers.
Re:An ex-ARM engineer critiques RISC-V
by pizlonator on Sunday November 01, 2020 @03:48PM
(#24962384)
Yeah exactly!
And worth noting that these are just the ones where you usually have good sequences on other cpus, but even then (like signed mul) they’re not perfect. Lots of room for improvement. It’s just that risc-v didn’t seize the opportunity.
You need fast sequences for all of these variants:
- add or sub or mul
- signed or unsigned
- 32 bit or 64 bit
Some of those need 5 instructions. I don’t remember which adventure you need to pick to get 5.