Re:DDR5 Is Coming: First 64GB DDR5-4800 Modules from SK Hynix
by CyberDildonics on Tuesday October 06, 2020 @11:33AM
(#24698796)
Why does it add a latency hop?
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Re:DDR5 Is Coming: First 64GB DDR5-4800 Modules from SK Hynix
by extropy on Tuesday October 06, 2020 @01:23PM
(#24700222)
At 5ghz, the signals travel only 4 cm each cycle (signal speed in copper is around 60% lightspeed).
Moving stuff further away means waiting multiple cycles for a reply.
Re:DDR5 Is Coming: First 64GB DDR5-4800 Modules from SK Hynix
by labawi on Tuesday October 06, 2020 @02:14PM
(#24700707)
Random article:
> Power10 chip .. using the DDR4 buffer chip from MicroChip and only adding a mere 10 nanoseconds to memory latency.
At 5GHz that would be 50 cycles or 1m round-trip. The delay is in processing - bridging logical and technical protocols, resynchronization, fanout, probably even a cache layer.