In fact, multiple gates can be created in the same transistor, in an effect SFN calls “multi-tunnel.” Multiple NOR and OR gates can thus be created from a single Bizen transistor, allowing creation of logic circuits with many fewer devices. This can result in a three-fold increase in gate density with a corresponding reduction in die size for integrated circuits based on the transistors. Summerland said that SFN is also creating a reduced device count processor architecture to enable analogue computing with Bizen transistors.
[0] https://www.eetimes.com/bipolar-zener-combo-takes-on-cmos/
In fact, multiple gates can be created in the same transistor, in an effect SFN calls “multi-tunnel.” Multiple NOR and OR gates can thus be created from a single Bizen transistor, allowing creation of logic circuits with many fewer devices. This can result in a three-fold increase in gate density with a corresponding reduction in die size for integrated circuits based on the transistors. Summerland said that SFN is also creating a reduced device count processor architecture to enable analogue computing with Bizen transistors.