This has been a thing with RF Chip design for the 30 years I've been paying attention. Transceiver I used 20 years ago consumed 220 mW in receive mode. One I used 10 years ago, 50 mW. Current one uses 10mW.
I can't come up with a single other example where cutting power was prioritized.
Things have tended to go the other way with die shrinks that favor performance and often with ridiculous amounts of overclocking piled on top of that.
>Brian and I have long been hinting at the sort of ridiculous frequency/voltage combinations mobile SoC vendors have been shipping at for nothing more than marketing purposes. I remember ARM telling me the ideal target for a Cortex A15 core in a smartphone was 1.2GHz. Samsung’s Exynos 5410 stuck four Cortex A15s in a phone with a max clock of 1.6GHz. The 5420 increases that to 1.7GHz. The problem with frequency scaling alone is that it typically comes at the price of higher voltage. There’s a quadratic relationship between voltage and power consumption, so it’s quite possibly one of the worst ways to get more performance.
The thing that I found interesting in the A14 is that this is the first time I can remember a chip designer using a die shrink mainly to cut power usage instead of increase performance.
However after Anandtech's recent deep dive into Tiger Lake performance testing, you can see where cutting power use in the A14 cores might be a winning move.
>Here we present the 15W vs 28W configuration figures for the single-threaded workloads, which do see a jump in performance by going to the higher TDP configuration, meaning [Tiger Lake] is thermally constrained at 15W even in ST workloads.
Comparing it against Apple’s A13, things aren’t looking so rosy as the Intel CPU barely outmatches it even though it uses several times more power, which doesn’t bode well for Intel once Apple releases its “Apple Silicon” Macbooks.
https://www.anandtech.com/show/16084/intel-tiger-lake-review...