AMX instructions are available in EL0 yes, and are used by CoreML and Accelerate.framework.
A sample instruction: 20 12 20 00... which doesn't in any stretch parse as a valid arm64 instruction in the Arm specification.
Edit: Some other AMX combinations off-hand:
00 10 20 00
21 12 20 00
20 12 20 00
40 10 20 00
Is it possible AMX is implemented with the implementation-defined system registers and aliases of SYS/SYSL in the encoding space reserved for implementation-defined system instructions? Do you have the encodings for the AMX instructions?