Re:AMD Announces Ryzen “Zen 3” and Radeon “RDNA2” Presentati...
by xxpor on Thursday September 10, 2020 @12:38PM
(#24433929)
Memory bandwidth is usually the bottleneck before PCIe.
You see this effect in other things too, such as Intel NICs being able to place packets directly in L3 cache because avoiding main memory is such a huge win (for both bandwidth and latency reasons):
You see this effect in other things too, such as Intel NICs being able to place packets directly in L3 cache because avoiding main memory is such a huge win (for both bandwidth and latency reasons):
https://www.intel.com/content/www/us/en/io/data-direct-i-o-t...