The vendors tools are notoriously buggy, don't conform to the HDL standard and lacks support to inference of some functional block (cascade DSPs and FIFOs for example).

Some FPGAs features are only available on yearly paid subscription. Also, the license is very restrictive, publishing benchmarking is not allowed, therefore, there is no public information on how to chose a computer to have faster synthesis.

Other than solving those issues, an open source framework enable the researches to search for newer place and route algorithms; enables new HDL languages to target the actual hardware instead of using verilog as intermediate language.