Re:Balancing AMD’s Future on the Edge of a Silicon Wafer
by jmole on Friday July 31, 2020 @04:51PM
(#24013886)
The demand is already booked at the fabs. This is an extra 50-100k on top of that.
Each chiplet (core complex die) on the AMD Epyc is 74 mm² plus the I/O die, which is built on a 12nm process is 125 mm². [0]
There is roughly 70k mm² of area on a 300mm wafer. Let's say for math's sake that after yield loss and so on, we end up with 37k mm^2 of chips that work; That's 500 chiplets per wafer.
Each CPU has 8 chiplets, so that's 62 CPUs per wafer.
So 50k CPUs is ~800 wafers and 100k CPUs is ~1600 wafers.
Cycle times for 7nm are ~80 days [1]
So you have at least an 80 day lead time, plus whatever time is spent waiting for open capacity.
TSMC capacity is said to be 130k wafers/month @ 7nm [2], so the volume needed is only ~1% of total monthly fab allocation. According to the same source, AMD already has ~20% allocation at TSMC, so it's 5% of AMDs total production for a single month for that order.
Each chiplet (core complex die) on the AMD Epyc is 74 mm² plus the I/O die, which is built on a 12nm process is 125 mm². [0]
There is roughly 70k mm² of area on a 300mm wafer. Let's say for math's sake that after yield loss and so on, we end up with 37k mm^2 of chips that work; That's 500 chiplets per wafer.
Each CPU has 8 chiplets, so that's 62 CPUs per wafer.
So 50k CPUs is ~800 wafers and 100k CPUs is ~1600 wafers.
Cycle times for 7nm are ~80 days [1]
So you have at least an 80 day lead time, plus whatever time is spent waiting for open capacity.
TSMC capacity is said to be 130k wafers/month @ 7nm [2], so the volume needed is only ~1% of total monthly fab allocation. According to the same source, AMD already has ~20% allocation at TSMC, so it's 5% of AMDs total production for a single month for that order.
[0] - https://en.wikichip.org/wiki/amd/microarchitectures/zen_2#Co... [1] - https://semiengineering.com/battling-fab-cycle-times/ [2] - https://wccftech.com/amd-7nm-wafer-production-set-to-double-...