Making transistors and connections is a bit like Minecraft: you need blocks to create structures and in this case the blocks are atoms of semiconductors.

It means that, leaving whatever physics considerations aside, the size of structures is limited by the size of the building blocks.

1 nm is about 5 silicon atoms so cannot be physically shrunk much further. I suspect that there are further physics limitations (e.g. you may be an isolation channel to be wide enough to actually isolate by preventing things like tunneling, etc.)

I got that. Just what is the process of actually making chips smaller and smaller until the limit would eventually be met.

Each additional step requires solving a lot of new engineering problems and usually some new physics too, and it's not a linear process: many techniques are proposed that become cost effective only when previous techniques hit their size limits, and then a lot of research is done and most techniques are never gotten to work at scale and just a few pan out and become the next process.

This is a great talk on the history of chip processes: https://www.youtube.com/watch?v=NGFhc8R_uO4

This is about some of the challenges that had to be solved for a current modern process: https://www.youtube.com/watch?v=f0gMdGrVteI

I'm not expert. I think lithographic processes are very important.

That's why companies like ASML are so critical. The technology to work at these scales and wavelengths is very tricky.

From Wikipedia: "ASML manufactures extreme ultraviolet lithography machines that produce light in the 13.3-13.7 nm wavelength range. A high-energy laser is focused on microscopic droplets of molten tin to produce a plasma, which emits EUV light." (that's UV close to the X-ray range...)