Re:The Arm Morello Board (2019)
by fanf2 on Wednesday July 01, 2020 @07:39PM
(#23708173)
If I understand correctly, this is going to be the first custom silicon implementation of a CHERI-style capability architecture. So far the CHERI-MIPS and CHERI-RISC-V implementations have been FPGA-only.
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| on HN ]
That is correct. We have FPGAs, qemu, and formal models (that can boot an OS) of CHERI-RISC-V and CHERI-MIPS. Most software development uses qemu as it is faster than the FPGAs at around 100MHz.
Having something in the GHz range will give us a chance to try things we are currently struggling with, e.g. fuzzing is painfully slow.