We (University of Cambridge) have added it to MIPS and RISC-V. As the same team did both of these they feel similar. Arm is working closely with us to add it to their architecture, but it has a few differences, mostly to allow for experimentation to see what should be added to the future production architecture.
Re:The Arm Morello Board (2019)
by waste_monk on Wednesday July 01, 2020 @10:31PM
(#23709345)
Let's hope this Morello CHERI experiment is fruitful.
> A Portable Architectural Protection Model ... We have experimented with adding the CHERI protection model to a number of ISAs, beginning with 64-bit MIPS, which was the baseline for our original research. More recently, we have developed an experimental version for 64-bit ARMv8-A (in collaboration with Arm), and also for 32/64-bit RISC-V.
Something that can work across architectures will see much faster adoption, I'm happy to see it.
[1] https://www.cl.cam.ac.uk/techreports/UCAM-CL-TR-941.pdf