Examining ARM vs. x86 Memory Models with Rust

Re:Examining ARM vs. x86 Memory Models with Rust by ajross on Saturday June 27, 2020 @09:24AM (#23661717)

I don't follow your point. Ordering control is necessarily a feature of the cache layer. You're right that there are local pipeline effects too, but if you have a memory ordering requirement in your architecture it has to be built into the cache design all the way up and down the hierarchy.

In practice that's the stuff that's expensive.

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Re:Examining ARM vs. x86 Memory Models with Rust by BeeOnRope on Saturday June 27, 2020 @09:28AM (#23661734)

I'm saying that everyone making CPUs uses a strongly ordered cache coherency subsystem and re-ordering only comes from "pipeline effects" [1].

Slightly longer version of the same claim here:

https://news.ycombinator.com/item?id=23661588

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[1] I prefer the term core-local because I think it's somewhat more accurate as it can include things like the delayed processing of invalidations and sibling core interactions in SMT which might not fall under "pipeline" effects but are still local to the (physical) core.

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Re:Examining ARM vs. x86 Memory Models with Rust by ajross on Saturday June 27, 2020 @10:20AM (#23661984)

That may well be true in ARM application processors, at least between CPUs. Though nothing in the architectural memory model guarantees that so I'd be surprised if there weren't some surprises (DMA on most of those CPUs is upstream of the cache, for example, and not susceptible to that kind of optimization).

I can guarantee it's not for "everyone making CPUs". I'm literally writing code as we speak on a multi CPU cache-incoherent system. It's a big world.

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Re:Examining ARM vs. x86 Memory Models with Rust by jeffreygoesto on Saturday June 27, 2020 @12:01PM (#23662609)

TriCore by any chance? ;-)

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Re:Examining ARM vs. x86 Memory Models with Rust by ajross on Saturday June 27, 2020 @12:14PM (#23662675)

Xtensa

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