Examining ARM vs. x86 Memory Models with Rust

Re:Examining ARM vs. x86 Memory Models with Rust by Diggsey on Saturday June 27, 2020 @08:05AM (#23661276)

One thing omitted from this article is that it's not only the physical hardware that may (effectively) re-order operations. The compiler may also perform these re-orderings.

The compiler's re-orderings will always be valid according to the abstract memory model rather than the hardware's, so even on x86 you must use the correct memory orderings, or risk subtle bugs due to compiler optimisations.

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Re:Examining ARM vs. x86 Memory Models with Rust by comex on Saturday June 27, 2020 @01:32PM (#23663178)

In particular, the “multi-threaded using volatile” example is technically incorrect because the compiler is allowed to move non-volatile accesses across volatile ones. [1] To make it correct (but still only on x86), you’d have to use std::sync::atomic::compiler_barrier.

[1] https://gcc.gnu.org/onlinedocs/gcc/Volatiles.html

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