Re:Why Apple ditched PowerPC, and what it says about Apple d...
by wolfgke on Sunday June 21, 2020 @09:07AM
(#23591803)
> Sure, but that's them having a competent (well, less incompetent) ISA
Have you looked at the encoding of Thumb-2 (T32) and particularly A64 (their newly designed instruction set for 64 bit)? Their instruction encoding is in my opinion much more convoluted than x86.
Re:Why Apple ditched PowerPC, and what it says about Apple d...
by DuskStar on Saturday June 20, 2020 @05:43PM
(#23587583)
> they delivered lower price for (say) 64 cores worth of performance, by putting them all on the same chunk of silicon.
Arguably AMD did the exact opposite - lower prices via splitting a processor into multiple pieces of silicon. (Chip price scale exponentially with area at the high end)
Re:Why Apple ditched PowerPC, and what it says about Apple d...
by a1369209993 on Saturday June 20, 2020 @06:24PM
(#23587916)
Well, my point there was that a 64-core CPU is not (significantly) higher performance than 64 single-core CPUs, so multi-core is - if a improvement at all - a price improvement, not a performance improvement, but fair point about the price-vs-area scaling.
Re:Why Apple ditched PowerPC, and what it says about Apple d...
by ido on Sunday June 21, 2020 @01:28AM
(#23590063)
Sure, but that's them having a competent
(well, less incompetent) ISA and microarchitecture
Hasn't x86 been basically RISC-like internally since the pentium-pro/amd k6? Is the translation layer that big of a hindrance?
Re:Why Apple ditched PowerPC, and what it says about Apple d...
by blattimwind on Sunday June 21, 2020 @09:49AM
(#23592002)
ISA doesn't matter nearly as much as people think, unless it's something really different (like VLIW/EPIC/...).
Also Intel and AMD have not delivered higher performance via more cores; they delivered lower price for (say) 64 cores worth of performance, by putting them all on the same chunk of silicon (edit: or at least in the same package). (There are some slight improvements in inter-processor interrupt and cache-forwarding latency, but if that's a performance bottleneck, the problem is bad parallelization at the code level.)