Re:Open source process design kit for usage with SkyWater Fo...
by bsder on Tuesday June 16, 2020 @06:00PM
(#23544803)
That design used X-FAB proprietary digital standard cells, I/O cells, analog IP, and SRAM.
Basically, they used XFAB to do the detailed design and extraction of the blocks. And then they assembled the blocks via place and route.
They also didn't push the technology very hard so they could get away with simple static timing analysis. 100MHz in 180nm for a really simple RISC is ridiculously slow--PowerPC chips were 100MHz+ in 500nm.
You will note that for EMIR drop--nothing. For signal integrity--nothing. Extraction and DRC is Magic--that's ... laughable is being nice.
Don't get me wrong, this is a great achievement. Pulling all these pieces together is really difficult.
However, we have been able to do this much for almost a decade+ now. I remember a different European initiative that did similar projects. The difference was that it tried to go after the analog blocks, as well. It failed for lack of accurate extraction.
The whole movement flounders on DRC and extraction. Without those, you cannot do the detailed design and analysis to build the fundamental blocks that you need to make interesting chips.
Basically, they used XFAB to do the detailed design and extraction of the blocks. And then they assembled the blocks via place and route.
They also didn't push the technology very hard so they could get away with simple static timing analysis. 100MHz in 180nm for a really simple RISC is ridiculously slow--PowerPC chips were 100MHz+ in 500nm.
You will note that for EMIR drop--nothing. For signal integrity--nothing. Extraction and DRC is Magic--that's ... laughable is being nice.
Don't get me wrong, this is a great achievement. Pulling all these pieces together is really difficult.
However, we have been able to do this much for almost a decade+ now. I remember a different European initiative that did similar projects. The difference was that it tried to go after the analog blocks, as well. It failed for lack of accurate extraction.
The whole movement flounders on DRC and extraction. Without those, you cannot do the detailed design and analysis to build the fundamental blocks that you need to make interesting chips.