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A comment on VexRiscv is a quadcore, Linux-capable RISC-V softcore for FPGA. Parent comment

Re:VexRiscv is a quadcore, Linux-capable RISC-V softcore for... by zozbot234 on Thursday May 21, 2020 @06:35PM (#23266323)
Don't general purpose CPU's and μC's use replaceable microcode as part of the chip implementation? Shouldn't that boil down to the same thing?
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Re:VexRiscv is a quadcore, Linux-capable RISC-V softcore for... by jimktrains2 on Thursday May 21, 2020 @08:09PM (#23267196)
The microcode is still controlling a microprocessor, not defining gates. It's more like microcode is the assembly language and the x86 or w/e is byte code.
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