Re:Single Writer Principle (2011)
by ncmncm on Monday May 11, 2020 @08:44PM
(#23149316)
"Not quite true", here, meaning not false. Hardware sequencing differs in detail from mutexes, but has to solve many of the same problems, ultimately much the same way. If your atomic-swap fails, you have to loop and try again, which absolutely counts as a stall, particularly counting your branch misprediction. A mutex ever held much longer than that mispredicted loop would indicate poor design.
And, of course, a single-writer ring buffer is entirely different in character. Writes cannot stall, and readers can work wholly in parallel without contention of any kind. (Multi-writer ring buffer? Good one.) New Intel chips have an instruction for a reader to sleep waiting on a cache invalidation, allowing the other hyperthread to run unimpeded by its partner's spin loop.
Lapping is easy to detect with a generation counter if needed, but anyway it is better just to keep up. Detected, being lapped is generally a system failure anyway.
And, of course, a single-writer ring buffer is entirely different in character. Writes cannot stall, and readers can work wholly in parallel without contention of any kind. (Multi-writer ring buffer? Good one.) New Intel chips have an instruction for a reader to sleep waiting on a cache invalidation, allowing the other hyperthread to run unimpeded by its partner's spin loop.
Lapping is easy to detect with a generation counter if needed, but anyway it is better just to keep up. Detected, being lapped is generally a system failure anyway.