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Re:IBM doubles its 14nm EDRAM density, adds hundreds of mega... by BeeOnRope on Sunday March 08, 2020 @10:52PM (#22522547)
I wouldn't really count the fill buffer between L1 and L2 as a separate caching level, or at least if you wanted to do that you should do something similar for L2 <-> L3, L3 <-> memory controller, etc: since such buffers or queues will exist at all those places.
Re:IBM doubles its 14nm EDRAM density, adds hundreds of mega... by blattimwind on Monday March 09, 2020 @10:59AM (#22525895)
L1 Fill Buffers are somewhat special at least on Intel because a memory read can be satisfied from these before the data is written into L1.