You have to switch to a higher-voltage state to account for the voltage droop that you will cause when the AVX units fire off.

https://travisdowns.github.io/blog/2020/01/17/avxfreq1.html

(specifically: https://travisdowns.github.io/assets/avxfreq1/fig-volts256-1... )

> So one theory is that this type of transition represents the period between when the CPU has requested a higher voltage (because wider 256-bit instructions imply a larger worst-case current delta event, hence a worst-case voltage drop) and when the higher voltage is delivered. While the core waits for the change to take effect, throttling is in effect in order to reduce the worst-case drop: without throttling33 there is no guarantee that a burst of wide SIMD instructions won’t drop the voltage below the minimum voltage required for safe operation at this frequency.

I assume this is due to AVX2 being rare in general-purpose software, so the design "one core is running AVX2 -> switch large part of CPU to AVX2 mode" doesn't hinder use cases where you are hammering all cores with AVX2 code.