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A comment on ARM64 CPUs speculatively execute instructions after ERET. Parent comment
- https://cpu.fyi/d/047#G6.11222648
- https://cpu.fyi/d/047#E9.CHDHDDBE
along with the Consumption of Speculative Data Barrier (CSDB): https://cpu.fyi/d/047#G9.10257993
But, as noted elsewhere in this thread, the canonical choice in most systems is DSB/ISB. Just one or the other isn't sufficient because they synchronize different things.
The canonical barriers on other platforms are LFENCE (x86) and SYNC (PowerPC).
For more references, see:
- https://github.com/google/safeside/blob/5fb6f00f/demos/asm/m...
[disclosure: I work on the Safeside project and wrote cpu.fyi as a side project]
https://github.com/mmdriley/cpu.fyi
- https://cpu.fyi/d/047#G6.11222648
- https://cpu.fyi/d/047#E9.CHDHDDBE
along with the Consumption of Speculative Data Barrier (CSDB): https://cpu.fyi/d/047#G9.10257993
But, as noted elsewhere in this thread, the canonical choice in most systems is DSB/ISB. Just one or the other isn't sufficient because they synchronize different things.
The canonical barriers on other platforms are LFENCE (x86) and SYNC (PowerPC).
For more references, see:
- https://github.com/google/safeside/blob/5fb6f00f/demos/asm/m...
- https://github.com/google/safeside/blob/5fb6f00f/demos/asm/m...
- https://github.com/google/safeside/blob/5fb6f00f/demos/asm/m...
[disclosure: I work on the Safeside project and wrote cpu.fyi as a side project]