An FPGA is a lot slower than a real ASIC in the same process node (one order of magnitude of slowdown at the very least - even two is far from uncommon!). OTOH, this means you can make an ASIC version of your logic in older process nodes that can be fabbed a lot cheaper than anything on the cutting edge, and still come out quite a bit ahead over the FPGA itself. This turns FPGA's into tools for quickly iterating on a design and little else, because for real use ASICs are just too good of a deal to pass up.

But this can only be fully realized if the "high-level" part of ASIC design becomes a lot more straightforward than it is today. Which in turn requires significant progress in open source EDA tooling.