Ideally there would be a standard way to verify and measure all the various firmware images (and potentially option ROMs which would be theoretically measured with SRTM via UEFI) for these system processors during boot during a DRTM event (with Intel's STM/AMD SMM supervisor enabled as well) but there is a long way to go for that.
[1] https://i.blackhat.com/USA-19/Wednesday/us-19-Hasarfaty-Behi...
[2] https://www.youtube.com/watch?v=iYvhHey_dTk
[3] https://chromium.googlesource.com/chromiumos/platform/ec/+/m...
> an “external ME” would be just fine running without a CPU socketed in at all
and made Ryzen a nearly-SoC, EPYC an actual SoC (no chipset at all required AFAIK). (To be fair Intel did integrate many things onto the die as well..)
https://fuse.wikichip.org/news/1177/amds-zen-cpu-complex-cac... seems to confirm that SMUs are on-die at least on EPYC.
> Interestingly the Chromebook EC firmware is open source
And even the Google Security Chip is included under that. You can't run a customized GSC firmware on a production device unless you have Google's keys, but you can look — and hopefully maybe reproduce the build?
It's worrying that these vulnerabilities are not disclosed in a way that lets people take control of their devices.
That the ME is so tightly integrated seems mainly to be for cost savings. There is also an argument for increased security, as now your attacker must be able to work with a decapped highly integrated CPU.
Intel did at one point do what you were suggesting -- if you look at the sandsifter project the author found a family of devices that had a parallel execution unit that was dispatched instructions with a "secret" prefix that had full access to memory. This could still exist in newer processors but be better hidden, it would certainly make a lot of one might want to do with the ME a lot easier.
[1]https://en.wikipedia.org/wiki/Intelligent_Platform_Managemen...
iLO is kind of a piece of crap, but I do love my Xen and resource pools
Keeping that "Just buy a shitload of cheap-o eBay 2U/4U hand-me-downs" workflow viable for years to come :D
I suspect this popped up in meetings and is at least partly the reason for the design now.
In other words, the ME is to Intel boards as Apple’s T2 chip is to their recent notebooks: an SoC that takes on the real role of being the “system processor”, turning the [rest of the] socketed CPU into effectively an “application processor.”
In fact, given that it’s so self-sufficient, it’s interesting that Intel choose to ship the ME as an “IP core” of the CPU itself, rather than making it part of the off-die Intel PCH chipset that they supply to mobo vendors. Is it just to provide the ME with low-latency access to CPU components like ALUs (for TPM encryption circuits) and d-cache (for packet sniffing)? Because it seems like it isn’t really built this way, and an “external ME” would be just fine running without a CPU socketed in at all. (Which would be neat, honestly; if you could exploit an external ME, you could run software on your Intel-chipset motherboard without a “real” CPU!)
Given that industry players seem to be all trending toward this design in one way or another (even game consoles did the “system SoC” / “application CPU” split with the last two generations), I wonder if this design pattern will ever be standardized, in the way that interrupt controllers or MMUs were standardized. Will we ever see an open-hardware board with its own open-hardware system-management SoC running FOSS firmware?