Re:AMD Ryzen 9 3950X Review
by mjevans on Thursday November 14, 2019 @04:15PM
(#21539506)
It would be interesting if we moved back to the final layer of cache being off-core, likely within the IO die or attached as additional chips within the package. That should decrease the core size, improve yields, and allow for differentiation in L3 size as well.
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Re:AMD Ryzen 9 3950X Review
by gameswithgo on Thursday November 14, 2019 @04:41PM
(#21539758)
but it would add latency :(
but maybe an L4 cache, off core, as additional chips!
At some point both higher latencies and deeper cache hierarchies seem inevitable: http://www.ilikebigbits.com/2014_04_21_myth_of_ram_1.html
Though, perhaps 3D integration can stave that off for many more generations.
Interestingly, Broadwell-S and Broadwell-R did this using the "Crystal Well" L4 cache.
However, DDR4 memory now provides more bandwidth than the L4 could (although probably at a higher latency).