RISC-V OS Using Rust: Memory Management Unit

Re:RISC-V OS Using Rust: Memory Management Unit by monocasa on Monday November 04, 2019 @06:55PM (#21448122)

There's no reason to sigh, it is a pretty goofy thing to both specify the bits as separate from the permissions, and check them, but not fill them out.

Going through RISCS I've implemented MMU code for:

MIPS - Has what they call a Dirty bit, but no separate RO bit, the dirty bit is really the ~RO bit.

SH* - See MIPS (lol, that could be their tagline)

Sparc - Doesn't really specify an MMU, but the "Reference MMU" does specify that the Modified bit (AKA the Dirty bit) is filled in by the MMU

PowerPC - Referenced and Changed bits in the PTEs are updated by the MMU.

ARM - Doesn't specify any A&D like construct.

Am I missing any? I can't think of an arch off the top of my head that has separate A&D from RWX, and doesn't have the MMU fill them in for you. Well other than RISC-V, lol.

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Re:RISC-V OS Using Rust: Memory Management Unit by Taniwha on Monday November 04, 2019 @11:17PM (#21449563)

Vax's had modified bits, 68030s had both (dirty managed in software), 80x896s have both [an 'unnamed' risc architecture (I worked on) had both, managed in software]

The big advantage of handling this stuff in software is that any hardware doing this has to go through the system caches which is just really messy - better to use the existing coherent paths already provided and provide hardware support so you don't have to do this often

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Re:RISC-V OS Using Rust: Memory Management Unit by comex on Tuesday November 05, 2019 @04:29AM (#21450923)

ARM (both 32-bit and 64-bit) does have an access bit, which, like RISC-V, can be either hardware managed or treated as an extra 'valid' bit.

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