Intel hardware accelerators sit on the PCIe bus, and burn just as much memory bandwidth as software encryption. The dataflow is basically:

  - disk DMA writes page from disk into DRAM
  - CPU (or PCIe crypto accel DMA) reads page from DRAM
  - CPU (or PCIe crypto accel DMA) writes encrypted page to DRAM
  - NIC DMA reads encrypted page from DRAM

Nothing changes from a memory bandwidth standpoint if its the CPU or a PCIE device doing those middle 2 steps. With "NIC TLS" (eg, inline hardware TLS) accelerators that sit on the NIC, those 2 middle steps can be eliminated, and condensed to the pre-crypto dataflow

   - disk DMA writes page from disk to DRAM
   - NIC DMA reads page from DRAM to NIC