IBM Adds POWER9 AIO, Pushes for an Open Memory-Agnostic Interface

Re:IBM Adds POWER9 AIO, Pushes for an Open Memory-Agnostic I... by drewg123 on Monday November 04, 2019 @10:30AM (#21442511)

Multiple Mellanox or Chelsio 100GbE NICs in an LACP bundle.

The 220g is from a prototype with a Rome CPU in a Naples-designed motherboard, with 4 Mellanox ConnectX-4 100GbE NICs. 2 of them are limited to Gen 3 x8 (since it is a Naples generation mobo).

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Re:IBM Adds POWER9 AIO, Pushes for an Open Memory-Agnostic I... by Teknoman117 on Monday November 04, 2019 @02:54PM (#21445728)

I'm curious about you being limited to 220 Gb/s on an AMD Rome box. The maximum theoretical DDR4 bandwidth on such a system with 3200 MT DDR4 is 204 GiB/s, so you'd only be using ~15% of the DRAM bandwidth assuming the block/record/file size of the cached data you're serving is enough to mask the DRAM latency.

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