Interesting, but seems that even fully developed, it would be limited to cases of when only a (lower requirement) portion of a chip needed online reconfigurability. Even one of the mailing list messages admits the routing is severely limited compared to the host, and timing hadn't been characterized. (that "ascii bitstream" format is quite cute)

If one was to flesh this idea out and create a "universal bitstream" -> specific FPGA "compiler", at what layer do we stop and declare that we have reached the proper primitive abstractions? What happens when technology moves on from those primitives, and more performance is demanded by the majority of the applications? An older CPU can go about its business a bit slower while an older FPGA trying to run new code won't even fit the design.