Re:TSMC: 3nm EUV Development Progress Going Well
by atq2119 on Saturday September 21, 2019 @10:25AM
(#21035551)
Chips are built in layers, with the actual transistors being in the (lower) base layers and the wiring being the (upper) metal layers. The metal layers themselves form a stack with layers with thin wires at the bottom and layers with very wide wires at the top. These wide wires are used because they have less resistance and therefore allow faster and longer-range data transmission across the chip. They are wide enough that EUV won't be used there for a long time (if ever).
Re:TSMC: 3nm EUV Development Progress Going Well
by emn13 on Monday September 23, 2019 @02:41AM
(#21046454)
But even the base layers aren't all EUV yet, at least not in the first gen EUV-enabled processes, or is that a misunderstanding?
At least I thought DUV was still in use in combination with (not entirely replaced by) EUV.
Re:TSMC: 3nm EUV Development Progress Going Well
by atq2119 on Monday September 23, 2019 @07:28AM
(#21047827)
Yes, that was precisely my point: a mix of EUV and DUV is used because the upper layers don't need EUV and DUV is cheaper and more mature.
Furthermore, it seems likely that the uppermost layers will never use EUV and that therefore a mix of EUV and DUV will always be used, indefinitely. This seems likely unless EUV surprisingly becomes much cheaper so that unifying on a single technology becomes worth it, or unless both EUV and DUV are replaced by something else entirely.
Just because a bike has a few carbon fiber spokes doesn't mean it's the same as another bike with a few carbon fiber spokes. The rest matters too, not least of which the other spokes ;-) and there are probably differences between carbon fiber spokes too!