Cerebras Systems unveils a 1.2T transistor chip for AI

Re:Cerebras Systems unveils a 1.2T transistor chip for AI by paulsutter on Monday August 19, 2019 @02:02PM (#20740104)

He was asking about the implications for yields. Do you route around bad dies/cores, and what are the implication for programming and performance?

For everyone else: normally a wafer is divded into dies, each of which (loosely) are a chip. Yield is a percentage of good parts and it's very unlikely that an entire wafer is good. Gene Amdahl estimated that 99.99% yield is needed for successful wafer scale integration:

https://en.wikipedia.org/wiki/Wafer-scale_integration

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Re:Cerebras Systems unveils a 1.2T transistor chip for AI by Veedrac on Monday August 19, 2019 @02:20PM (#20740270)

> For example, the typical 300mm wafer from TSMC may contain “a modest hundred number of flaws,” said Feldman. Cerebras gave its Swarm interconnect redundant links to route around defective tiles and allocated “a little over 1% [of the tiles] as spares.”

https://www.eetimes.com/document.asp?doc_id=1335043&page_num...

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