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A comment on RISC Is Unscalable. Parent comment

Re:RISC Is Unscalable by gnode on Monday July 29, 2019 @09:51AM (#20554555)
Although the micro-operations are dispatched to many parallel execution units, so it's really better described as VLIW.
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Re:RISC Is Unscalable by jasonwatkinspdx on Monday July 29, 2019 @03:55PM (#20558687)
No, that's just superscalar. The defining feature of VLIW is that the the compiler schedules the dispatch.
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Re:RISC Is Unscalable by Erwin on Monday July 29, 2019 @04:48PM (#20559269)
The ports/schedulers have quite different capabilities however:

https://en.wikichip.org/wiki/intel/microarchitectures/skylak...

Using the Intel Vtune tools you can see how each port is utilized, so you could in theory change your code to mix instructions for best utilization beyond what reordering the CPU can do itself, so I can see some analogy with building a VLIW instruction group.

There's a crazy amount of performance counters you can look at (the perf tool can do that too, but just try running "perf list" to view available counters).

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