I have not read the paper yet but the abstract says that they compared two hardware adders synthesized from C++ code. It seems like a fair comparison but I wonder whether it might be possible to hand design a much more efficient posit adder that is more competitive with hand designed floating point adders. I can see how the number of lookup tables used in synthesis would be proportional to the number of gates used on a dedicated chip though so maybe there would be no difference in comparing hand optimized adders on ICs.