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A comment on MIPS R3000. Parent comment
But the big reason is that except for the case of simple, short pipeline designs like the early MIPS parts they make designing CPUs annoying too.
The second you introduced parallel decode or a branch predictor with more than a cycle of latency these things hurt and don't help.
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But the big reason is that except for the case of simple, short pipeline designs like the early MIPS parts they make designing CPUs annoying too.
The second you introduced parallel decode or a branch predictor with more than a cycle of latency these things hurt and don't help.