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A comment on Universal Logic Gates (2015). Parent comment

Re:Universal Logic Gates (2015) by analognoise on Monday June 17, 2019 @02:05PM (#20205734)
Of course after you do the minimization, you move to a technology mapping step that takes these things into account.

"the fact that your DNF PAL circuit might just be two layers of NAND (equivalent to a layer of AND feeding into an OR layer) is kind of an implementation detail, isn't it?"

No. That's absolutely, 100% fundamental.

It's called "Canonical Form" https://en.wikipedia.org/wiki/Canonical_normal_form

It's canonical for a reason.

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Re:Universal Logic Gates (2015) by kragen on Thursday June 20, 2019 @06:20PM (#20237979)
It seems that you didn't understand my comment well enough to respond to it, maybe due to a lack of domain knowledge.
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Re:Universal Logic Gates (2015) by analognoise on Saturday June 22, 2019 @04:17PM (#20251518)
Sure, what's a good reference?
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