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A comment on Ara: A 1 GHz+ Scalable and Energy-Efficient RISC-V Vector Processor. Parent comment

Re:Ara: A 1 GHz+ Scalable and Energy-Efficient RISC-V Vector... by ryacko on Saturday June 08, 2019 @12:32PM (#20133293)
No, it would scale logarithmically if you want to minimize latency.
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Re:Ara: A 1 GHz+ Scalable and Energy-Efficient RISC-V Vector... by atq2119 on Saturday June 08, 2019 @02:40PM (#20134201)
It cannot scale logarithmically because you need at least a linear number of gates to represent the inputs.

It doesn't have to scale superlinearly either, because the natural circuit using a linear number of adders is already of a logarithmic depth, which is best possible asymptotically.

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Re:Ara: A 1 GHz+ Scalable and Energy-Efficient RISC-V Vector... by ncmncm on Friday June 21, 2019 @01:14AM (#20240043)
The gate depth scales logarithmically, and that determines how many cycles it takes, or (worse) how fast your cycles can be, if you want the answer in one cycle.
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Re:Ara: A 1 GHz+ Scalable and Energy-Efficient RISC-V Vector... by ryacko on Saturday June 08, 2019 @07:10PM (#20135810)
A lot of complexity could be eschewed if processors weren't faster than 100 Mhz.
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