Re:Free Wolfram Engine for Developers
by palmerdabbelt on Thursday May 23, 2019 @01:21PM
(#19993753)
All of SiFive's chips use Chisel, it's our primary design language. We use commercial tools post-Verilog (ie, synthesis and place+route). We use Verilator for some simulation, but also use commercial Verilog simulators.
We have chips shipping in volume.
I’m aware of chisel used to verify some RISC-V cores that were fabricated, but that’s a research POC, not a volume/production ASIC.