Register latency is usually around 4ns (2.5-3.5 Ghz with a pipeline depth of 12-16). The article claims main memory latency is 7x more, which is around 24ns to 45ns. I tried to come up with plausible numbers that fix the 7x ratio they mention.

These days main memory latencies are more around 70-80ns (single sockets) and 80-100 ns (dual sockets).

Being off by so much does make me wonder about the accuracy of the rest of the article.