For now, the vast majority of RV CPUs will go into embedded CPUs, where an extension is a compile switch away.
In practice, I think all embedded CPUs will be RV32IMAC.
For bigger CPUs, it's pretty simply: almost all them will be RV64GC.
ISA fragmentation is nothing new: x86 and ARM don't seem to have a problem with them, and one could easily argue that those are way more fragmented than RV right now.
Or RV32IMAC+some extension that makes sense for the application.
There's also a non-defined but planned RV32E for embedded.
>RV64GC
I suspect this will be the case at first, then a superset will take over.
e.g. bitfield operations extension and vector extension are unlikely not to be taken advantage of by e.g. Debian. Likely resulting in a few arch variants with increasingly more such extensions, such as further adding DSP and JIT extensions.
It should be a bit messy at first, and calm down later when there's a lot of frozen extensions that handle most popular tasks.
If anything, I fear calling the 'G' subset was premature. That we're already talking about RV64GC and not just RV64G does strongly point to that.
You probably don't need to same code to run on such differing hardware though. The value is in your code working on 2 processors with optional FPUs.
I don't think you're ever going to get to USB levels of plug and play, but you don't really need that.
Edit: So yes you might get usb 3/c/whatever levels of confusion, but you don't swap processors multiple times a day so not really a problem.
RV32I is nothing close to RV64IMAFDQCPBS. It seems like all the fragmentation standards are made to avoid packaged up as a "standard" to make sure everything under the sun can use risc-v.
(see also usb-c)