ARM has those things but MIPS, once this process is completed, will be open source. This makes a difference regarding license pay.

Also you can modify the instruction set, which you cannot do with Arm. Risc-V has a detailed model of which bits you can change,what is the common core and so on, which Mips will need too.

ARM has vendor extension space as well. Intel used that for DSP and "Wireless MMX" in their Xscale CPUs.

Depending on what the license actually will be. ARM has for example presented "free" cores to fight against RISC-V. Free as in slightly cheaper beer.

https://www.bit-tech.net/news/arm-responds-to-risc-v-threat-...

Yes, and so to some extent so does RISC-V. Some RISC-V ISA extensions are still under development, but getting getting stable. Also the RISC-V is in comparison to MIPS a cleaner ISA. No delay slots for example.

Are there delay slots in modern / 64-bit MIPS? I've heard they're only really present in very old MIPS

Good question. I took a look. What is being released is the Release 6 ISA. And I stand corrected, according to wikipedia that ISA doesn't have delay slots:

MIPS32/MIPS64 Release 6 in 2014 added[22] the following:

    a new family of branches with no delay slot:
        unconditional branches (BC) and branch-and-link (BALC) with a 26-bit offset,
        conditional branch on zero/non-zero with a 21-bit offset,
        full set of signed and unsigned conditional branches compare between two registers (e.g. BGTUC) or a register against zero (e.g. BGTZC),
        full set of branch-and-link which compare a register against zero (e.g. BGTZALC).
    index jump instructions with no delay slot designed to support large absolute addresses.
    instructions to load 16-bit immediates at bit position 16, 32 or 48, allowing to easily generate large constants.
    PC-relative load instructions, as well as address generation with large (PC-relative) offsets.
    bit-reversal and byte-alignment instructions (previously only available with the DSP extension).
    multiply and divide instructions redefined so that they use a single register for their result).
    instructions generating truth values now generate all zeroes or all ones instead of just clearing/setting the 0-bit,
    instructions using a truth value now only interpret all-zeroes as false instead of just looking at the 0-bit.

Removed infrequently used instructions:

    some conditional moves
    branch likely instructions (deprecated in previous releases).
    integer overflow trapping instructions with 16-bit immediate
    integer accumulator instructions (together HI/LO registers, moved to the DSP Application-Specific Extension)
    unaligned load instructions (LWL and LWR), (requiring that most ordinary loads and stores support misaligned access, possibly via trapping and with the addition of a new instruction (BALIGN))

Reorganized the instruction encoding, freeing space for future expansions.

https://en.wikipedia.org/wiki/MIPS_architecture#MIPS32/MIPS6...

seems until very recently it still had delay slots[1]

[1] https://en.m.wikipedia.org/wiki/MIPS_architecture (see mips64 release 6)