To build on what you're saying: while true from the user perspective, out-of-order execution and instruction level parallelism means there are some types of parallelism happening at the single core level. However, these systems are designed to produce results to the end user as though no micro-level parallelism is occurring.

I mention this mainly because I've recently discovered the joy of SIMD intrinsics. While it's pretty difficult to gain anything from out-of-order execution (cough other than a spectre) it's possible to take advantage of SIMD through compiler autovectorization, intrinsics, or assembly coding. SIMD doesn't have the problem of race conditions though as the parallel operations are non-conflicting and the user view of the computation is synchronous. I imagine under the hood there are all kinds of tricks at play for complex instructions that involve different microcircuits that take different numbers of cycles.

EDIT: clarified last sentence

SMT (Like Intel's hyperthreading) can actually run 2 different instructions from 2 different processes in the same clock cycle on a single core.